Introduction Building upon the IIR filter from the last post we’re now going to improve the edge/peak detection fpga module.
Why The current algorithm is really simple, maybe too simple: whenever the ADC value is above (resp. below) a hardcoded value, it outputs 1 (resp. 0) with hysteresis.
There are two problems with that:
well first, the hardcoded values… For some reason no one has really complained about it so far (?